In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The receiving bus nodes recognize the signal as being high or low using receivers, also referred to as input buffers. Often the receiver is a differential receiver, i.e., a receiver that detects the difference between two input signals, referred to as the differential inputs. These input signals may be a received signal and a reference voltage or they may be a received signal and the inverse of the received signal. In either case, it is the difference between the two input signals that the receiver detects in order to determine the state of the received signal.
Integrated circuits are powered at certain voltage levels, which levels are then provided to the various components, such as the receivers, which are located on the integrated circuit. However, the nominal supply voltage for integrated circuits keeps being decreased to reduce power consumption. Additionally, fluctuations of the voltage level during operation can make the voltage level powering a receiver even lower. The lower the supply voltage, the more challenging it is to get a receiver to operate reliably.
The signal frequency at which communication occurs can limit the performance of the overall system. Thus, the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to be reliably recognized at the receiving bus nodes as being high or low. Characteristics that affect the time in which a signal is recognized by a receiver include the set up time of the receiver, i.e., the amount of time before a clock edge that a signal must arrive and settle to a recognized level, and the hold time of the receiver, i.e., the time that the received signal must stay at a certain level in order for that level to be detected.
The amount of setup and hold depends on the speed of the circuit and the skew and jitter of the clock distribution mechanism. The setup and hold time requirement decreases as the transistor speed increases because the process feature size decreases. However, historically, skew and jitter of the clock distribution mechanism does not decrease as fast as the clock speed increases. As a proportion of the clock frequency, skew and jitter now take up a larger and larger percentage of the clock cycle time. Additionally, as the process feature size shrinks the transistor speed increases faster than the delay in interconnects. For signals that need to be distributed through a long interconnect (wire) the receiver of that signal at the beginning of the long wire receives the signal earlier (have a better setup time) than the receiver at the end of the long wire because of interconnect delay.
On the other hand, the receiver at the beginning of the long wire has worse hold time (premature signal switching) than the receiver at the end of the long wire. The end result is extra guard-banding is needed when quantifying setup and hold timing and this guard band, like jitter and skew and the delay of interconnect, becomes a larger and larger percentage of the clock cycle time.
Referring to FIG. 1, a conventional write driver (10) outputs two signals (wd and {overscore (wd)}) through delays (12a and 12b) to a switch (14). The switch (14) also receives a clock signal (clk) that controls whether the write driver data is output onto the global bitline (gbl) and its complement ({overscore (gbl)}). As is conventionally understood, the two output signals (wd and {overscore (wd)}) are complements unless the circuit is in a precharge or reset state. Those skilled in the art will also appreciate that the switch (14) may receive a clock-derived signal rather than the clock signal itself.
Referring to FIG. 2, a typical write driver (10) and delay stage (12) is shown. The write driver (10) consists of two sets of transistors, which produce the output signals (wd and {overscore (wd)}) respectively. Specifically, the set of transistors producing the output signal (wd) includes a p-channel transistor (22a), a p-channel transistor (24a), and an n-channel transistor (26a). The p-channel transistor (22a) receives the clock signal (clk) at the gate, is connected at the source to pull-up voltage (Vcc), and is coupled drain to drain with p-channel transistor (24a). The p-channel transistor (24a) is also connected to pull-up voltage (Vcc) at the source, and is coupled gate to gate with n-channel transistor (26a). The n-channel transistor (26a) receives an input signal (Vin) at the gate, and at the source is coupled through pull-down transistor (28) to ground (GND). The pull-down transistor receives the clock signal (clk) at the gate, is coupled to n-channel transistor (26a) at the drain, and connected to ground (GND) at the source.
The set of transistors producing ({overscore (wd)}) are connected similarly, wherein transistors 22b, 24b, and 26b have the same interconnections as 22a, 24a, and 26a respectively. As can be seen, however, the input signal received by n-channel transistor (26b) passes through inverter (30) to become ({overscore (Vin)}). Thus, the output of the two sets of transistors are complements (wd and {overscore (wd)}). The output signals (wd and {overscore (wd)}) are fed to the delay stage (12), which, for example, consists of two pairs of inverters (38a, 38b and 37a, 37b) and (38c, 38d and 37c, 37d) respectively.
In general, in one aspect, the present invention involves a system for minimizing the effect of clock skew in a bit line write driver comprising a first control circuit coupled to the bit line write driver; and a second control circuit coupled to the bit line write driver. The bit line write driver outputs a first output signal and a second output signal; the first control circuit receives feedback from the second output signal and controls whether the bit line write driver outputs the first output signal based on the feedback from the second output signal; and the second control circuit receives feedback from the first output signal and controls whether the bit line write driver outputs the second output signal based on the feedback from the first output signal.
In general, in one aspect, the present invention involves a method of minimizing the effect of clock skew in a bit line write driver comprising outputting a first signal and a second signal from the bit line write driver; controlling the outputting of the second signal from the bit line write driver based on feedback of the first signal; and controlling the outputting of the first signal from the bit line write driver based on feedback of the second signal.
In general, in one aspect, the present invention involves an apparatus for minimizing the effect of clock skew in a bit line write driver comprising means for outputting a first signal and a second signal from the bit line write driver; means for controlling the outputting of the second signal from the bit line write driver based on feedback of the first signal; and means for controlling the outputting of the first signal from the bit line write driver based on feedback of the second signal.
In general, in one aspect, the present invention involves a bit line write driver with minimized clock skew effect, comprising a first set of transistors for producing a first output signal, a second set of transistors for producing a second output signal; a first control circuit for controlling whether a first output signal is output from the bit line write driver based on feedback from the second output signal; and a second control circuit for controlling whether a second output signal is output from the bit line write driver based on feedback from the first output signal.
In general, in one aspect, the present invention involves an apparatus for minimizing the effect of clock skew on a bit line write driver, comprising a first set of transistors for producing a first output signal, a second set of transistors for producing a second output signal; a first delay for delaying the first output signal; a second delay for delaying the second output signal; a first control circuit for controlling whether a first output signal is output from the bit line write driver based on feedback from the delayed second output signal; a second control circuit for controlling whether a second output signal is output from the bit line write driver based on feedback from the delayed first output signal, and an inverter for inverting the input signal to produce the inverted input signal.
The first set of transistors comprising a first p-channel transistor; a second p-channel transistor; and a first n-channel transistor. The first p-channel transistor is connected gate to a clock signal, source to a pull-up voltage, and drain to drain with the second p-channel transistor. The second p-channel transistor is connected source to the pull-up voltage, and gate to gate with the first n-channel transistor. The first n-channel transistor is connected gate to an input signal, and source to drain with a pull-down transistor. The pull-down transistor is connected gate to the clock signal, and source to ground.
The second set of transistors comprises a third p-channel transistor; a fourth p-channel transistor; and a second n-channel transistor. The third p-channel transistor is connected gate to the clock signal, source to the pull-up voltage, and drain to drain with the fourth p-channel transistor. The fourth p-channel transistor is connected source to the pull-up voltage, and gate to gate with the third n-channel transistor. The third n-channel transistor is connected gate to an inverted input signal, and source to drain with the pull-down transistor.
The first control circuit comprises a first control p-channel transistor; and a first control n-channel transistor. The first control p-channel transistor is connected gate to the feedback of the delayed second output signal, source to a pull-up voltage, and drain to drain with the first p-channel transistor and the second p-channel transistor. The first control n-channel transistor is connected gate to the feedback of the delayed second output signal, drain to drain with the first control p-channel transistor, the first p-channel transistor, and the second p-channel transistor, and source to the drain of first n-channel transistor.
The second control circuit comprises a second control p-channel transistor; and a second control n-channel transistor. The second control p-channel transistor is connected gate to the feedback of the delayed first output signal, source to a pull-up voltage, and drain to drain with the third p-channel transistor and the fourth p-channel transistor. The second control n-channel transistor is connected gate to the feedback of the delayed first output signal, drain to drain with the second control p-channel transistor, the third p-channel transistor, and the fourth p-channel transistor, and source to the drain of second n-channel transistor.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.